A fundamental design challenge in creating a memory cell of an electrically erasable programmable read only memory (EEPROM) device is to use a controllable and reproducible electrical effect that has sufficient non-linearity so that the memory cell (1) can be written to (or erased) at one voltage in less than one millisecond (1 ms) and can be read at another voltage, and (2) the data within the memory cell must remain unchanged for more than ten (10) years.
Prior art stacked/split gate EEPROM technology requires (1) special multi-polysilicon materials, (2) different gate oxide thicknesses, and (3) modified doping profiles. These prior art requirements create process complexity and high cost when embedded into a complementary metal oxide semiconductor (CMOS) process.
FIG. 1 illustrates a schematic diagram of a prior art memory cell 100 of a single poly erasable programmable read only memory (EEPROM) device. Memory cell 100 comprises one P-channel metal oxide semiconductor (PMOS) transistor 110 and one P-channel metal oxide semiconductor (PMOS) capacitor 120. The PMOS capacitor 120 is formed by connecting together the source, drain and substrate of a PMOS transistor. A cross sectional view 200 of the memory cell 100 is shown in FIG. 2.
The PMOS transistor 110 may be referred to as PMOS program transistor 110. The PMOS capacitor 120 may be referred to as PMOS control capacitor 120. The gate of the PMOS program transistor 110 and the gate of the PMOS control capacitor 120 are connected together (i.e., shorted together) and are isolated from the other active elements. The shorted gates of the PMOS program transistor 110 and the PMOS control capacitor 120 are collectively referred to as a “floating gate” 130. Charges (in amounts that represent either a zero (0) representation or a one (1) representation) may be written to the floating gate 130. In order to avoid well bias interference, the PMOS program transistor 110 and the PMOS control capacitor 120 are each located in a separate N well.
The prior art memory cell 100 is written to by injecting drain avalanche hot electrons into the floating gate 130. For PMOS operation (as shown in FIG. 1 and in FIG. 2) low voltage is applied to the control gate and drain of PMOS control capacitor 120 and high voltage is applied to the source/well of PMOS program transistor 110. The channel PMOS program transistor 110 is turned on and hot electrons are generated at the high electric field region at the drain junction (designated “Vinj” in FIG. 1). With positive voltage on the control gate of PMOS control transistor 120, some hot electrons with high energy will pass through the silicon-silicon dioxide (Si—SiO2) potential barrier and be injected into the floating gate 130.
The prior art memory cell 100 is erased by applying a high voltage to the control gate of the PMOS control transistor 120 and to the ground drain and source of the PMOS program transistor 110. Electrons on the floating gate 130 will pass through the gate oxide between the floating gate 130 and the control gate of the PMOS control capacitor 120 by Fowler-Nordheim (FN) tunneling process and go to the substrate.
During programming, most control gate voltage should be coupled between the floating gate 130 and the drain/source of the PMOS program transistor 110 to facilitate electron injection to the floating gate 130 but not further to the control gate of the PMOS control transistor 120. This requires the capacitance between the floating gate 130 and the control gate to be large. On the other hand, during the erase procedure, more control gate voltage should be coupled between the floating gate 130 and the control gate, so that electrons can tunnel from the floating gate 130 to the substrate by the Fowler-Nordheim (FN) tunneling process. This requires the capacitance between the floating gate 130 and the control gate to be small.
These two contradictory requirements for the control gate capacitance during the program procedure and the erase procedure leave a narrower operation window. This results in poor data retention and slower speeds for an EEPROM that comprises one PMOS program transistor and one PMOS control capacitor.
To improve the operational speed and data retention for a single poly EEPROM device, EEPROM designers have sometimes placed an additional capacitor in the basic memory cell. This approach has one large capacitor for the programming operation and one small capacitor for the erase operation. Capacitor coupling techniques are used to achieve a favorable electric field for both the programming operation and the erase operation.
The floating gate of an added capacitor has to be filled with hot electrons. Hot electrons that pass through gate oxide will create oxide damage. Oxide damage degrades the endurance of a memory cell. Endurance is measured by how many program/erase cycles the gate oxide can tolerate before unacceptable damage occurs. Therefore, one major drawback to adding an extra capacitor is that it degrades EEPROM memory cell endurance performance.
Another drawback to adding an extra capacitor is that it significantly increases the size of the basic memory cell. This significantly lowers the EEPROM density. Additional chip area is required for the extra capacitors. This increases the cost.
Another drawback of prior art CMOS EEPROM technology is the speed of the programming procedure. The programming procedure is carried out by utilizing drain avalanche hot electrons. Because the efficiency of generating and injecting the drain avalanche hot electrons is low, programming times are relatively long. The programming time is usually one hundred milliseconds (100 ms) or longer. Even the improved coupling provided by using additional capacitors only reduces the programming time to about twenty milliseconds (20 ms).
Therefore, there is a need in the art for an improved system and method for providing an improved high density electrically erasable programmable read only memory (EEPROM) device. In particular, there is a need in the art for an improved system and method for achieving a favorable electric field for both the programming operation and the erase operation of a memory cell in an EEPROM device without employing an additional capacitor in the memory cell.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.